SN74HC166N

HC series, 74HC166, parallel to serial, serial to serial, 1 element, 8 bits, DIP

When it is high, SH/LD\ enables serial data input and couples eight flip-flops for serial shifting with each CLK pulse. When it is low, the parallel data input is enabled, and the synchronous load occurs on the next clock pulse. During parallel loading, the serial data stream is disabled. The clock is realized through a 2-input positive NOR gate on the low-to-high edge of CLK, allowing one input to be used as a clock enable or clock suppression function. Keeping CLK or CLK INH high will disable the clock, and keeping either low will enable the other clock input. This allows the system clock to run freely, and the registers can be stopped according to commands input from other clocks. Only when CLK is high, should CLK INH be changed to high.